Pick a stage to begin. Each stage focuses on one part of the converter — the highlighted component in each schematic shows what you'll be designing. All parameters carry through between stages.
STAGE 1PLANT & BODEDefine operating point, switching frequency and parasitics. The whole power path defines the small-signal plant shown in the Bode plots.
Input Parameters
VIN ceiling
VIN(max) %
VIN(nom) %
VIN(min) %
VOUT ceiling
VOUT %
Vripple %
IOUT ceiling
IOUT %
ΔIL ripple %
fSW
DCR
ESR
Design Equations (CCM)
D = VOUT / VIN
ΔIL = (ripple%) × IOUT
L = VOUT(VIN−VOUT) / (VIN·fSW·ΔIL)
worst-case across VIN range
C = ΔIL / (8·fSW·(ΔVOUT−ΔIL·ESR))
capacitive + ESR ripple budget
Bode Transfer Function
Gdc(VIN) = VOUT / VIN
ZL = jωL + DCR
ZC = 1/(jωC) + ESR
H(jω) = Gdc · (ZC‖Rload) / (ZL+ZC‖Rload)
Duty Cycle & Ripple Detail
Losses & Efficiency
Bode — Magnitude
VIN(max)VIN(nom)VIN(min)
Bode — Phase
VIN(max)VIN(nom)VIN(min)
STAGE 2INDUCTORSelect a core material and geometry, pick wire gauge, and verify the inductor against saturation and copper / core losses.
Stage 1 — Inductor Physical Design. Starting from the required inductance L and peak current Ipk computed on the Plant tab, select a core material and geometry, then compute the number of turns N, peak flux density B̂, wire gauge, and core losses. The design is based on field energy storage equivalence: ½LI²pk must equal the energy storable in the core.
From Plant Tab (live)
Core Material
Material Family
Core Geometry
Load preset (optional)
mm²
mm
mm³
mm²
mm
Winding Parameters
Max fill factor
Current density J (A/mm²)
Air gap (for gapped ferrite)
Inductor Design Equations
Energy: ½LI²pk = ½B²Ve/µ₀µeff
N = L·Ipk / (Bmax·Ae)
or N = √(L / AL) from datasheet AL
B̂ = L·Ipk / (N·Ae)
AL = µ₀·µeff·Ae / le
Pcore = k·fα·ΔBβ·Ve (Steinmetz)
ΔB = L·ΔIL / (N·Ae)
Inductor Design Results
Core Saturation Margin
Loss Breakdown
Wire Selection
STAGE 3OUTPUT CAPPick a capacitor technology, then compute parallel count to meet capacitance, ESR, and ripple-current requirements.
Stage 2 — Output Capacitor Selection. Starting from the minimum capacitance and ESR budget from the Plant tab, select a capacitor technology and compute the number of capacitors needed in parallel to meet both the capacitance and ESR requirements, plus ripple current rating.
From Plant Tab (live)
Capacitor Technology
Capacitor Parameters
Single cap value
Voltage rating
Single cap ESR (mΩ)
Ripple current rating (A rms)
Capacitor Selection Results
Parallel Combination Summary
Derating & Margin
STAGE 4MOSFETPick RDS(on) and gate-charge figures for the high-side and low-side switches; compute conduction and switching losses.
Stage 3 — MOSFET Selection & Loss Analysis. Specify high-side and low-side MOSFET parameters. The tool computes conduction loss, switching loss, gate drive loss, body diode loss, and total power dissipation — then feeds everything back into the system efficiency.
From Plant Tab (live)
High-Side MOSFET (Q1)
RDS(on) (mΩ)
Qg total (nC)
tr rise time (ns)
tf fall time (ns)
Coss (pF)
VGS drive (V)
Low-Side MOSFET (Q2 — Synchronous)
RDS(on) (mΩ)
Qg total (nC)
Body diode VF (mV)
Dead time (ns)
MOSFET Loss Analysis
System Efficiency (All Losses)
MOSFET Stress & Ratings Check
STAGE 5CONTROLLERDesign a Type II / III compensator: set crossover and phase margin, then verify the closed-loop response on the Bode plot.
Stage 4 — Closed-Loop Controller & Stability. Design a Type II or Type III compensator to close the loop around the plant transfer function. Set your crossover frequency and phase margin targets, and the tool computes compensator zeros/poles, then overlays the loop gain T(s) = Gc(s)·Gplant(s) on the Bode plot with gain/phase margin readouts.
Plant Summary (live from Tab 1)
Compensator Type
Design Targets
Crossover fc (fraction of fSW)
Target phase margin (°)
PWM modulator gain Vramp (V)
Type III Extra Pole/Zero
2nd zero placement (× f0)
2nd pole placement (× fc)
Compensator Equations
Gmod = 1/Vramp (PWM modulator)
T(s) = Gc(s) · Gmod · Gplant(s)
Type II:
Gc(s) = (Gc0/s)·(1+s/ωz)/(1+s/ωp)
Type III:
Gc(s) = (Gc0/s)·∏(1+s/ωzi)/∏(1+s/ωpi)
Zeros placed near f₀ to boost phase; poles at high freq to roll off